1. Field of Invention
The present invention relates to analog to digital converters and more specifically to the calibration of analog to digital conveners.
2. Description of Related Art
Advances in integrated circuit technology produce smaller and smaller devices. Circuits shrink, chips become smaller or contain more function. Maintaining the same accuracy and resolution in circuits such as analog to digital converters (ADC) become a greater challenge. As the devices grow smaller the offset voltage of the comparator circuits used convert the analog signal into the first stage of conversion to a digital signal grow larger.
U.S. Pat. No. 5,594,612 (Henrion) shows an ADC that has digital linearity correction. A calibration signal is generated using a digital to analog converter (DAC) and converted by an ADC to a digital signal that has been compensated in accordance with compensation coefficients. The compensation coefficients are adjusted in response to distortion components. In U.S. Pat. No. 5,218,362 (Mayes et al.) a multi-step digital to analog converter is described with an embedded correction memory for trimming resistor ladders to correct for non-uniformities in the resistance of the ladder network.
In FIG. 1a is shown an ADC of prior art where a resistor string 10 with multiple tap points 11 is used to supply a plurality of reference voltages to a plurality of comparators 12. An analog input voltage Vin 13 is connected to one input of the comparators 12 while the reference voltage from the multi-tap resistor string is connected to the other input to the comparators 12. The outputs of the comparators are connected to a decoder which creates a digital output 16. In FIG. 1b is shown the input stage of the comparators. An offset voltage occurs in the differential input stage when the threshold voltage Vt1 does not equal Vt2. To compensate for this offset voltage, which could vary significantly from chip to chip, the reference voltage applied to the comparator needs to be changed from its ideal value.
In FIG. 2a is another ADC of prior art. Here a track and hold circuit (T/H) 20 is selected by a T/H selector 21 and a DAC 22 under the control of data from a memory 23 program a voltage into the track and hold circuit 20 which compensates non-linearities caused by offset voltages of transistors. A calibration voltage applied as Vin is compared to the voltage on the track and hold circuits 20 in the comparators 25. The track and hold circuit 20 on each of the comparators 25 are adjusted by the DAC until the digital output 27 of the decoder 26 produces an accurate representation of the input analog voltage 24 to within a least significant bit, or fraction of a least significant bit by using a more accurate DAC. In FIG. 2b is shown an equivalent representation of the track and hold circuit 25. When the selector 21 selects a track and hold circuit 20 switch 30 is closed allowing the DAC 22 to charge capacitor 31 to a reference voltage. After the switch is opened, charge on capacitor 31 begins to be lost through leakage mechanisms as represented by the current source 32. As device geometries get smaller this leakage current 32 increases, requiring increased frequency of refresh to restore the voltage on the capacitor 31.
An ADC design is needed that can compensate for the characteristics of shrinking geometry""s, while benefiting from the higher productivity of the ever-evolving semiconductor technology. This ADC design would allow a calibration that lasts between calibration steps and compensates for the non-unformities caused by resistor networks and transistor threshold variations.
It is an objective of the present invention to provide a reference voltage to a comparator circuit of an ADC which compensates for non-uniformity""s that are cause by variations in the process that is used to manufacture the ADC.
It is also an objective of the present invention to provide a plurality of the reference voltages to a plurality of comparator circuits under control of memory cells in a matrix of selector elements.
It is further an objective of the present invention to provide various ways to layout the wiring from the taps of a resistor string to a set of selector elements connecting the reference voltages to the comparator circuits,
In the present invention an ADC is configured with a plurality of comparators comparing an input voltage to a plurality of reference voltages, one reference voltage connected to each comparator. The output of each comparator is connected to a decoder which produces a digital representation of the input voltage. The uniqueness of the present invention is in the method that the reference voltages are selected and connected to the comparators.
An Mxc3x97N matrix of selector elements connect a plurality of reference voltages to a plurality of voltage comparators. The matrix is arranged with M rows of N selector elements. Within each selector element a memory cell controls a switch that is connected between the input and output terminals of the selector element. The output terminals of a row of selector elements are connected together and to the reference input of a comparator. Each row on the Mxc3x97N matrix of selector elements is connected to a separate comparator. A different reference voltage is connected to each selector element in a row, and when a memory cell selects a switch to be on, or selected, the reference voltage connected to the selector element is connected to the reference input of the comparator. The switches in the selector elements are selected to be on or off depending upon data stored in a memory cell that is connected to each switch. The memory cell can be constructed from a variety of cell technologies such as SRAM, DRAM, FLASH and not excluding other technologies. A range of reference voltages is connected to the selector elements in each row. The reference voltages can be created by any means that will provide a wide range of voltages that are incrementally a small voltage difference apart. A resistor string connected between two bias voltages with a plurality of voltage taps is but one way to provide the necessary reference voltages. The range of voltages provided in small increments allow the reference voltage to the comparator to be selected such that non-linearities caused by process variations in such parameters as transistor threshold voltage to be compensated in order to provide a more accurate compare to the ADC input voltage. This is accomplished by selecting a reference voltage for a particular comparator that is above or below an xe2x80x9cidealxe2x80x9d voltage to compensate for such process variations as differences in threshold voltage.
In the present invention an Mxc3x97N matrix of selector elements arranged in M rows and N columns is used to connect reference voltages to a plurality of comparators. Each switch within the selector elements is controlled on or off depending upon data stored in a memory cell contained within each selector element. There is a row of selector elements for each comparator, and a first terminal of each selector element in a row is connected together and then connected to the reference input to a comparator circuit, A second terminal of each selector elements is connected to a tap in a resistor string which is connected between two bias voltages. The connecting wire to a resistor tap is routed across the matrix of selector elements in such a way as to connect one selector element in each row that is crossed by the resistor tap wire. The taps on the resistor string are in increments that allow the ADC to resolve an input voltage to a portion of the least significant bit (LSB). Depending upon what the specified resolution of the ADC is, the taps on the resistor string could for example be every LSB, every half LSB every fourth of an LSB or any other convenient fraction of an LSB. The number of selector elements in a row connected to the resistor string is dependent upon the increments of the taps on the resistor string and the amount of variation in circuit parameters that is compensated by the ability to select au incremental range of reference voltages. A particular reference voltage is connected to selector elements in more than one row to allow the range of voltages necessary compensate for variations in key parameters, such as threshold voltage.
A plurality of first level wiring is connected to a fit terminal of N of Mxc3x97N selector elements. The first level wiring connects the first terminals of the selector elements to a first terminal of a plurality of comparators. The second terminal of the plurality of comparators is connected to the analog to digital converter (ADC) input voltage. A plurality of second level wiring connects a plurality of reference voltages to the second terminal of a plurality of selector elements and to the second terminal of only one selector element in each tow. The number of selector elements connected by the second level wiring is at most M. Assuming the first level wiring is primarily in the X direction, the second level wiring uses both the X and the Y direction to route the plurality of wires connecting the second terminals of a plurality of selector elements, one in each row, together and further connected to a reference voltage. Depending on the resolution of the ADC, the plurality of the second level wiring will connect to selector elements in every Z adjacent columns, where Z=1, 2, and 4 to produce a resolution of one LSB (least significant bit), one half LSB and one fourth LSB respectively.